● A PCIe 2.0 Gen 1 to Multi I/O (4S, 2S+1P, 2S+SPI, LB) Controller with 4S, 2S+1P, 2S+SPI, 2S, 1S, Local Bus, and GPIO support
● PCI Express
-- Single-lane (X1) PCI Express Endpoint Controller with PHY integrated
-- Compliant with PCI Express Base Specification Revision 2.0
-- Compliant with PCI Express Card Specifications
-- Compliant with PCI Bus Power Management Interface Specification V1.2
-- Supports 4 PCI Express Functions
-- Supports both Legacy and MSI Interrupt
-- Supports ASPM Power Management
-- Supports Expansion ROM feature through external SPI Flash
● Serial Port Interface
-- Supports up to 4 UARTs
-- Supports RS-232/RS-422/RS-485 Multiprotocol
-- Supports Auto-Hardware and Auto-Software Flow Control
-- Supports 5, 6, 7, 8 and 9-bit Serial Communication
-- Supports Even, Odd, None, Space and Mark Parity
-- Supports Custom Baud Rates (up to 25Mbps) by internal PLL or external clock
-- Supports 256 Bytes Transmitter/Receiver FIFOs each port
-- Supports Remote Wakeup and Power Management
-- Supports UART Transceiver Shutdown mode
-- Supports Slow IrDA mode (up to 115,200bps)
-- Supports 9-bit Multi-drop Communication
-- Supports DMA Burst Transfer
● Parallel Port Interface
-- Compatible with IEEE 1284 – SPP/Nibble/Byte/ECP modes
● SPI Master Interface
-- Programmable SPI Clock Frequency up to 41.6MHz
-- Supports 4 SPI Timing modes (Mode 0/1/2/3)
-- Supports MSB/LSB First Transfer fashion
-- Support MISO Late Sampling
-- Programmable device Chip Select, up to 8 SPI devices
-- Supports Non-Burst-Type Transfer (up to 8 bytes), and Burst-Type Transfer via DMA mode for high performance
-- Supports to fragment large data block into several smaller transfers on SPI bus
-- Supports Burst Type with OP-code transfer
-- Supports external pin wakeup
● Local Bus Interface
-- Supports Memory or I/O access via BAR0/BAR1
-- Supports Direct access and Bus Master (DMA) access
-- Supports Asynchronous or Synchronous modes
-- Supports 8-bit or 16-bit data bus width (Little Endian and Big Endian bus swap)
-- Supports Multiplexed Address/Data (up to 64KB address space) and Separated Address/Data (up to 32KB address space) bus types
-- Supports “Slave Request based DMA” mode
-- Supports local bus clock output, up to 62.5MHz
-- Supports programmable INT0/INT1 Level/Edge Trigger
-- Supports external pins wakeup
● Supports I2C Master Interface
● Supports up to 24 Bi-directional GPIOs
● Integrates On-chip Power-on Reset Circuit
● On-chip 3.3V to 1.0V LDO Regulator
● 68-pin QFN 8x8mm, RoHS Compliant Package
● Operating Temperature Range: -40 to +85°C
